The well-established MOS family of semiconductors circuits has significantly improved the integration of a large number of circuits into a single chip. The speed of MOS circuits is enhanced by integrating P-channel (PMOS) and N-channel (NMOS) devices together to form CMOS circuits The operation of a CMOS circuit is optimized by forming a totem pole type of output structure, with the PMOS device connected to a supply voltage and the NMOS device connected to ground. The NMOS circuit provides optimum performance with regard to speed, when its backgate is connected to its semiconductor source terminal. In like manner, the backgate of the PMOS circuit is connected to its source terminal, and thus to the supply voltage.
Bipolar transistor devices are characterized by high switching speeds and large output currents, but cannot be formed with the circuit density of that of MOS circuits. While both families of transistor circuits have become independently and highly developed, little effort has been directed to the integration of the circuits together. Some approaches have been taken to integrate linear or analog bipolar and MOS circuits on the same chip in which digital MOS circuits are formed. A problem which arises from this type of integration is the different operating voltage range between each family of circuits. In order to provide proper junction isolation between the semiconductor substrate and other semiconductor regions formed therein, such substrate, if P-type, is generally connected to the most negative potential of the operating voltages. With linear bipolar circuits, or in other high voltage devices, the substrate is connected to a voltage which may be in the neighborhood of -10 to -15 volts. In integrated bipolar-CMOS circuits, such potential is also connected through the substrate to the backgate region of the NMOS circuits. When this occurs, the performance of the NMOS circuits are degraded. Moreover, the electric field generated across the gate insulators thereof may become excessive and damage the NMOS circuits. This problem does not occur in the PMOS circuits, as such circuits are generally formed in an N-well which becomes reverse biased with respect to the P-type substrate, thereby providing an automatic isolation.
From the foregoing, a need exists for a technique to integrate linear bipolar and CMOS and digital CMOS circuits together by utilizing certain bipolar structures for isolating the analog circuits, thereby permitting the P-type substrate to be connected to a negative voltage to benefit the digital CMOS operation, thus permitting the backgate region of the digital NMOS circuits to be connected to the source terminals thereof for optimum operation.